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general description the max5803/max5804 single-channel, low-power, 8-/10-/12-bit, voltage-output this is an addition to content digital-to-analog converters (dacs) include output buffers and an internal reference that is selectable to be 2.048v, 2.500v, or 4.096v. the max5803/max5804/ max5805 accept a wide supply voltage range of 2.7v to 5.5v with extremely low power (< 1mw) consumption to accommodate most low-voltage applications. a precision external reference input allows rail-to-rail operation and presents a 100ki (typ) load to an external reference. the max5803/max5804/max5805 have an i 2 c- compatible, 2-wire interface that operates at clock rates up to 450khz. the dac output is buffered and has a low supply current of 155 f a (typical at 3.5v) and a low offset error of q 0.5mv (typical). on power-up, the max5803/max5804/max5805 reset the dac outputs to zero, providing additional safety for applications that drive valves or other transducers which need to be off on power-up. the max5803/max5804/max5805 include a user- configurable active-low asynchronous input, aux for additional flexibility. this input can be programmed to asynchronously clear (clr) or temporarily gate (gate) the dac output to a user-programmable value. a dedicated active-low asynchronous ldac input is also included. this allows simultaneous output updates of multiple devices. the max5803/max5804/max5805 are available in 10-pin tdfn/max m packages and are specified over the -40nc to +125nc temperature range . applications programmable voltage and current sources gain and offset adjustment automatic tuning and optical control power amplifier control and biasing process control and servo loops portable instrumentation data acquisition benefits and features s single high-accuracy dac channel ? 12-bit accuracy without adjustments ? 1 lsb inl buffered voltage output ? guaranteed monotonic over all operating conditions s three precision selectable internal references ? 2.048v, 2.500v, or 4.096v s internal output buffer ? rail-to-rail operation with external reference ? 6.3s settling time ? output directly drives 2ki loads s small, 10-pin, 2mm x 3mm tdfn and 3mm x 5mm max packages s wide 2.7v to 5.5v supply range s fast 400khz i 2 c-compatible, 2-wire serial interface with readback capability s power-on-reset to zero-scale dac output s user-configurable asynchronous i/o functions: clr, ldac, gate s three software-selectable power-down output impedances: 1ki, 100ki, or high impedance s low 155a dac supply current at 3v 19-6464; rev 2; 6/13 ordering information appears at end of data sheet. max is a registered trademark of maxim integrated products, inc. functional diagram for related parts and recommended products to use with this part, refer to: www.maximintegrated.com/max5803.related addr sda scl out po r v dd gnd i 2 c serial interfac e code register dac control logic da c latch 100ki 1ki ref internal referenc e/ external buffe r v ddio aux ldac code clear / reset po r load gate clear / reset powe r down buffe r max5803 max5804 max5805 8- /1 0- / 12-bit da c max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com.
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 2 v dd to gnd ............................................................. -0.3v to +6v v ddio to gnd ......................................................... -0.3v to +6v out, ref to gnd ........ -0.3v to lower of (v dd + 0.3v) and +6v scl, sda, aux, ldac to gnd .............................. -0.3v to +6v addr to gnd ................................................... -0.3v to lower of (v ddio + 0.3v) and +6v continuous power dissipation (t a = +70nc) tdfn (derate 14.9mw/nc above +70nc) ............... 1188.7mw max (derate 8.8mw/nc above +70nc) .................. 707.3mw maximum continuous current into any pin .................... 50ma operating temperature range ........................ -40nc to +125nc storage temperature range ............................ -65nc to +150nc lead temperature (soldering, 10s) ................................ +300nc soldering temperature (reflow) ...................................... +260nc tdfn junction-to-ambient thermal resistance ( ja ) ....... 67.3nc/w max junction-to-ambient thermal resistance ( ja ) ..... 113.1nc/w junction-to-ambient thermal resistance ( jc ) ........... 42nc/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera- tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) electrical characteristics (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2ki , t a = -40nc to +125nc, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units dc performance (note 3) resolution and monotonicity n max5803 8 bits max5804 10 max5805 12 integral nonlinearity (note 4) inl max5803, 8 bits -0.25 0.05 +0.25 lsb max5804, 10 bits -0.5 0.2 +0.5 max5805, 12 bits -1 0. 5 +1 differential nonlinearity (note 4) dnl max5803, 8 bits -0.25 0.05 +0.25 lsb max5804, 10 bits -0.5 0.1 +0.5 max5805, 12 bits -1 0.2 +1 offset error (note 5) oe -5 0.5 +5 mv offset error drift 10 fv/nc gain error (note 5) ge -1.0 0.1 +1.0 %fs gain temperature coefficient with respect to v ref 2.5 ppm of fs/nc zero-scale error 0 +10 mv full-scale error with respect to v ref -0.5 +0.5 %fs maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 3 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2ki , t a = -40nc to +125nc, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units dac output characteristics output voltage range (note 6) no load 0 v dd v 2ki load to gnd 0 v dd - 0.2 2ki load to v dd 0.2 v dd load regulation v out = v fs /2 v dd = 3v q10%, |i out | p 5ma 300 fv/ma v dd = 5v q10%, |i out | p 10ma 300 dc output impedance v out = v fs /2 v dd = 3v q10%, |i out | p 5ma 0.3 i v dd = 5v q10%, |i out | p 10ma 0.3 capacitive load handling c l 500 pf resistive load handling r l 2 ki short-circuit output current v dd = 5.5v sourcing (output short to gnd) 30 ma sinking (output shorted to v dd ) 40 dynamic performance voltage-output slew rate sr positive and negative 2.0 v/s voltage-output settling time ? scale to ? scale, to p 1 lsb, max5803 2.8 s ? scale to ? scale, to p 1 lsb, max5804 5.2 ? scale to ? scale, to p 1 lsb, max5805 6.3 dac glitch impulse major code transition 5.0 nvs digital feedthrough code = 0, all digital inputs from 0v to v ddio 0.5 nvs power-up time startup calibration time (note 7) 200 fs from power-down mode 60 fs dc power-supply rejection v dd = 3v q10% or 5v q10% 100 fv/v maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 4 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2ki , t a = -40nc to +125nc, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units output voltage-noise density (dac output at midscale) external reference f = 1khz 88 nv/hz f = 10khz 79 2.048v internal reference f = 1khz 108 f = 10khz 98 2.5v internal reference f = 1khz 117 f = 10khz 110 4.096v internal reference f = 1khz 152 f = 10khz 145 integrated output noise (dac output at midscale) external reference f = 0.1hz to 10hz 10 fv p-p f = 0.1hz to 10khz 72 f = 0.1hz to 300khz 298 2.048v internal reference f = 0.1hz to 10hz 11 f = 0.1hz to 10khz 89 f = 0.1hz to 300khz 370 2.5v internal reference f = 0.1hz to 10hz 12 f = 0.1hz to 10khz 99 f = 0.1hz to 300khz 355 4.096v internal reference f = 0.1hz to 10hz 13 f = 0.1hz to 10khz 128 f = 0.1hz to 300khz 400 output voltage-noise density (dac output at full scale) external reference f = 1khz 113 nv/hz f = 10khz 100 2.048v internal reference f = 1khz 172 f = 10khz 157 2.5v internal reference f = 1khz 195 f = 10khz 180 4.096v internal reference f = 1khz 279 f = 10khz 258 integrated output noise (dac output at full scale) external reference f = 0.1hz to 10hz 12 fv p-p f = 0.1hz to 10khz 88 f = 0.1hz to 300khz 280 2.048v internal reference f = 0.1hz to 10hz 14 f = 0.1hz to 10khz 135 f = 0.1hz to 300khz 530 2.5v internal reference f = 0.1hz to 10hz 15 f = 0.1hz to 10khz 160 f = 0.1hz to 300khz 550 4.096v internal reference f = 0.1hz to 10hz 23 f = 0.1hz to 10khz 220 f = 0.1hz to 300khz 610 maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 5 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2ki , t a = -40nc to +125nc, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units reference input reference input range v ref 1.24 v dd v reference input current i ref v ref = v dd = 5.5v 55 75 fa reference input impedance r ref 75 100 ki reference ouput reference output voltage v ref v ref = 2.048v, t a = +25nc 2.043 2.048 2.053 v v ref = 2.5v, t a = +25nc 2.494 2.500 2.506 v ref = 4.096v, t a = +25nc 4.086 4.096 4.106 reference output noise density v ref = 2.048v f = 1khz 129 nv/hz f = 10khz 122 v ref = 2.500v f = 1khz 158 f = 10khz 151 v ref = 4.096v f = 1khz 254 f = 10khz 237 integrated reference output noise v ref = 2.048v f = 0.1hz to 10hz 12 fv p-p f = 0.1hz to 10khz 110 f = 0.1hz to 300khz 390 v ref = 2.500v f = 0.1hz to 10hz 15 f = 0.1hz to 10khz 129 f = 0.1hz to 300khz 430 v ref = 4.096v f = 0.1hz to 10hz 20 f = 0.1hz to 10khz 205 f = 0.1hz to 300khz 525 reference temperature coefficient (note 8) max5805a 4 12 ppm/nc max5803/max5804/max5805b 10 25 reference drive capacity external load 25 ki reference capacitive load handling 200 pf reference load regulation i source = 0 to 500fa 1.0 mv/ma reference line regulation 0.1 mv/v maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 6 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2ki , t a = -40nc to +125nc, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units power requirements supply voltage v dd v ref = 4.096v 4.5 5.5 v all other options 2.7 5.5 i/o supply voltage v ddio 1.8 5.5 v supply current (dac output at midscale) (note 9) i dd external reference v ref = 3v 135 190 fa v ref = 5v 165 225 internal reference, reference pin undriven v ref = 2.048v 190 265 v ref = 2.5v 205 280 v ref = 4.096v 250 340 internal reference, reference pin driven v ref = 2.048v 215 300 v ref = 2.5v 225 315 v ref = 4.096v 275 375 supply current (dac output at full scale) (note 9) i dd external reference v ref = 3v 155 210 fa v ref = 5v 200 265 internal reference, reference pin undriven v ref = 2.048v 205 280 v ref = 2.5v 220 300 v ref = 4.096v 275 375 internal reference, reference pin driven v ref = 2.048v 225 310 v ref = 2.5v 240 330 v ref = 4.096v 300 410 power-down mode supply current (dac powered down, reference remains active) (note 9) i dd internal reference, reference pin driven v ref = 2.048v 90 135 fa v ref = 2.5v 93 135 v ref = 4.096v 100 150 power-down mode supply current (note 9) i pd external reference, v dd = v ref 0.4 2 fa digital supply current (note 9) i ddio 1.0 fa digital input characteristics (scl, sda, addr, aux, ldac) input high voltage v ih 2.2v < v ddio < 5.5v 0.7 x v ddio v 1.8v < v ddio < 2.2v 0.8 x v ddio input low voltage v il 2.2v < v ddio < 5.5v 0.3 x v ddio v 1.8v < v ddio < 2.2v 0.2 x v ddio maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 7 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2ki , t a = -40nc to +125nc, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units hysteresis voltage v h 0.15 v input leakage current (note 9) i in 0.1 1 fa input capacitance c in 3 pf addr pullup/pulldown strength r pu , r pd (note 10) 30 50 90 ki digital output (sda) output low voltage v ol i sink = 3ma 0.2 v i 2 c timing characteristics (scl, sda, aux, ldac) scl clock frequency f scl 400 khz bus free time between a stop and a start condition t buf 1.3 s hold time repeated for a start condition t hd;sta 0.6 s scl pulse width low t low 1.3 s scl pulse width high t high 0.6 s setup time for repeated start condition t su;sta 0.6 s data hold time t hd;dat 0 900 ns data setup time t su;dat 100 ns sda and scl receiving rise time t r 20 + c b /10 300 ns sda and scl receiving fall time t f 20 + c b /10 300 ns sda transmitting fall time t f 20 + c b /10 250 ns setup time for stop condition t su;sto 0.6 s bus capacitance allowed c b v dd = 2.7v to 5.5v 10 400 pf pulse width of suppressed spike t sp 50 ns clr removal time prior to a recognized start t clrsta 100 ns clr pulse width low t clpw 20 ns ldac pulse width low t ldpw 20 ns ldac fall to sclk fall to hold t ldh applies to execution edge 400 ns maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 8 note 2: electrical specifications are production tested at t a = +25c. specifications over the entire operating temperature range are guaranteed by design and characterization. typical specifications are at t a = +25c. note 3: dc performance is tested without load. note 4: linearity is tested with unloaded outputs to within 20mv of gnd and v dd. note 5: gain and offset calculated from measurements made with v ref = v dd at code 30 and 4065 for max5805, code 8 and 1016 for max5804, and code 2 and 254 for max5803. note 6: subject to zero and full-scale error limits and v ref settings. note 7: on power-up, the device initiates an internal 200fs (typ) calibration sequence. all commands issued during this time will be ignored. note 8: specification is guaranteed by design and characterization. note 9: static logic inputs with v il = v gnd and v ih = v ddio . note 10: an unconnected condition on addr is sensed via a resistive pullup and pulldown operation; for proper operation, addr should be tied to v ddio, gnd, or left unconnected with minimal capacitance. figure 1. i 2 c serial interface timing diagram electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2ki , t a = -40nc to +125nc, unless otherwise noted.) (note 2) t su ;s to t r t sp t hd;sta t su;sta t f t high t hd;dat t low t clpw t clrsta t ldh t ldpw t hd;sta t f s s s r p sda scl clr ldac t su;dat t r t buf maxim integrated
9 typical operating characteristics (max5805, 12-bit performance, t a = +25nc, unless otherwise noted.) inl vs. code max5803 toc01 code (lsb) inl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 3v no load dnl vs. code max5803 toc04 code (lsb) dnl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 4096 v dd = v ref = 5v no load offset and zero-scale error vs. supply voltage max5803 toc07 supply voltage (v) error (mv) 5.1 4.7 3.9 4.3 3.5 3.1 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0 2.7 5.5 v ref = 2.5v (external) no load offset error zero-scale error inl vs. code max5803 toc02 code (lsb) inl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 5v no load inl and dnl vs. supply voltage max5803 toc05 supply voltage (v) error (lsb) 5.1 4.7 3.9 4.3 3.5 3.1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 2.7 5.5 min inl min dnl max dnl max inl v dd = v ref offset and zero-scale error vs. temperature max5803 toc08 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 error (mv) -0.8 -0.6 -0.4 -0.2 0.2 0 0.4 0.6 0.8 1.0 -1.0 v ref = 2.5v (external) no load offset error (v dd = 5v) offset error (v dd = 3v) zero-scale error dnl vs. code max5803 toc03 code (lsb) dnl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 4096 v dd = v ref = 3v no load temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 inl and dnl vs. temperature max5803 toc06 error (lsb) -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 min inl min dnl max dnl max inl v dd = v ref = 3v full-scale error and gain error vs. supply voltage max5803 toc09 supply voltage (v) error (%fs) 5.1 4.7 3.9 4.3 3.5 3.1 -0.09 -0.08 -0.06 -0.07 -0.05 -0.04 -0.03 v ref = 2.5v (external) no load -0.02 -0.10 2.7 5.5 gain error full-scale error max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 10 maxim integrated typical operating characteristics (continued) (max5805, 12-bit performance, t a = +25nc, unless otherwise noted.) 0.02 0.04 0.06 0.08 0.10 0.12 full-scale error and gain error vs. temperature max5803 toc10 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 error (%fsr) 0 v ref = 2.5v (external) no load gain error (v dd = 3v) full-scale error gain error (v dd = 5v) supply current vs. supply voltage (2.500v internal reference) max5803 toc13 supply voltage (v) supply current (a) 5.1 4.7 4.3 3.9 3.5 3.1 50 100 150 200 250 300 0 2.7 5.5 v dd = v ddio v dac = full scale no load dac off reference output only dac on reference pad driven dac on ext reference = 2.5v dac on reference pad undriven 50 100 150 200 250 300 350 0 supply current vs. code (for internal ref, pin is undriven) max5803 toc16 code (lsb) supply current (a) 3584 3072 2560 2048 1536 1024 512 0 4096 no load, t a = +25c v dd = v ref(ext) = 3v v dd = v ref(ext) = 5v v dd = 5v, v ref(int) = 4.096v v dd = 5v, v ref(int) = 2.048v v dd = 5v, v ref(int) = 2.5v supply current vs. temperature (pin undriven for internal ref modes) max5803 toc11 temperature (c) supply current (a) 110 95 -25 -10 5 35 50 65 20 80 140 180 220 260 300 340 380 100 -40 125 v dd = v ddio v dac_ = full scale dac enabled no load v ref = v dd = 3v v ref = v dd = 5v v ref = 2.5v, v dd = 3v v ref = 2.048v, v dd = 3v v ref = 4.096v, v dd = 5v supply current vs. supply voltage (4.096v internal reference) max5803 toc14 supply current (a) 50 100 150 200 250 300 350 400 0 supply voltage (v) 5.25 5.00 4.75 4.50 4.25 4.00 5.50 v dd = v ddio v dac = full scale no load dac off reference output only dac on reference pad driven dac on reference pad undriven i ref (external) vs. code max5803 toc17 code (lsb) supply current (a) 3584 3072 2560 2048 1536 1024 30 35 40 45 50 55 60 20 25 512 0 4096 v dd = v ref no load v ref = 5v v ref = 3v supply current vs. supply voltage (2.048v internal reference) max5803 toc12 supply voltage (v) supply current (a) 5.1 4.7 4.3 3.9 3.5 3.1 50 100 150 200 250 300 0 2.7 5.5 v dd = v ddio v dac = full scale no load dac off reference output only dac on reference pad driven dac on reference pad undriven power-down mode supply current vs. supply voltage max5803 toc15 power-down supply current (a) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 supply voltage (v) 5.1 4.7 4.3 3.9 3.5 3.1 2.7 5.5 v dd = v ref (external, active) t a = -40c t a = +85c t a = +25c t a = +125c
11 typical operating characteristics (continued) (max5805, 12-bit performance, t a = +25nc, unless otherwise noted.) settling to 1 lsb (v dd = v ref = 5v, r l = 2ki , c l = 200pf) max5803 toc18 v out 2v/div 2s / div zoomed v out 1 lsb/div trigger pulse 10v/div 1/4 scale to 3/4 scale 5.9s major code transition glitch energy (v dd = v ref = 5v, r l = 2ki , c l = 200pf) max5803 toc20 trigger pulse 5v/div zoomed v out 1.25mv/div 2s /div 1 lsb change (midcode transition 0x800 to 0x7ff) giltch impulse = 5nv*s v out vs. time transient exiting power-down max5803 toc22 0v 0v 20s /div 36th edge v dd = 5v, v ref = 2.5v external v clk 5v/div v out 1v/div settling to 1 lsb (v dd = v ref = 5v, r l = 2ki , c l = 200pf) max5803 toc19 zoomed v out 1 lsb /div trigger pulse 10v/div v out 2v/div 2s /div 6.3s 3/4 scale to 1/4 scale major code transition glitch energy (v dd = v ref = 5v, r l = 2ki , c l = 200pf) max5803 toc21 trigger pulse 5v/div zoomed v out 1.25mv/div 2s /div 1 lsb change (midcode transition 0x7ff to 0x800) giltch impulse = 5nv*s power-on reset to 0v max5803 toc23 0v 0v 40s /div v dd = v ref = 5v 10ki load to v dd v dd 2v/div v out 2v/div max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 12 maxim integrated typical operating characteristics (continued) (max5805, 12-bit performance, t a = +25nc, unless otherwise noted.) digital feedthrough (v dd = v ref = 5v, r l = 2ki , c l = 200pf) max5803 toc24 v out 125v/div 1s /div v dd = v ref = 5v dac at midscale digital feedthrough = 0.1nv*s output current limiting max5803 toc26 i out (ma) ?v out (mv) 40 30 10 20 -20 -10 0 -30 -400 -300 -200 -100 0 100 200 300 400 500 -500 -40 50 v dd = 3v v dd = 5v v dd = v ref midscale 0.1hz to 10hz output noise, external reference (v dd = 5v, v ref = 4.5v) max5803 toc29 v out 5v/div 4s /div midscale unloaded v p-p = 10v headroom at rails vs. output current (v dd = v ref ) max5803 toc27 i out (ma) v out (v) 9 8 6 7 2 3 4 5 1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 01 0 v dd = 5v, sourcing full scale v dd = 3v, sourcing full scale v dd = 3v and 5v sinking zero scale output load regulation max5803 toc25 i out (ma) ?v out (mv) 30 20 10 0 -10 -20 -2 -1 0 1 2 3 -3 -30 40 v dd = 5v v dd = 3v v dd = v ref midscale noise-voltage density vs. frequency (dac at midscale) max5803 toc28 frequency (hz) noise-voltage density (nv/ (hz)) 10k 1k 50 100 150 200 250 300 350 0 100 100k v dd = 5v, v ref = 4.096v (internal) v dd = 5v, v ref = 2.5v (internal) v dd = 5v, v ref = 2.048v (internal) v dd = 5v, v ref = 5v (external) 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 2.048v) max5803 toc30 v out 5v/div 4s /div midscale unloaded v p-p = 11v
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 13 maxim integrated typical operating characteristics (continued) (max5805, 12-bit performance, t a = +25nc, unless otherwise noted.) 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 2.500v) max5803 toc31 v out 5v/div 4s /div midscale unloaded v p-p = 12v device count 5 10 15 25 20 35 30 40 45 0 v ref drift vs. temperature max5803 toc33 temperature coefficient (ppm /c) 4.5 5.0 6.5 6.0 5.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 v dd = 2.7v v ref = 2.5v box method internal reference noise density vs. frequency max5803 toc35 frequency (hz) noise-voltage density (nv/ (hz)) 10k 1k 50 100 150 200 250 300 350 400 450 0 100 100k v ref = 4.096v v ref = 2.5v v ref = 2.048v 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 4.096v) max5803 toc32 v out 5v/div 4s /div midscale unloaded v p-p = 13v reference output current (a) ?v ref (mv) 400 300 200 100 -0.25 -0.20 -0.15 -0.10 -0.05 0 -0.30 0 500 reference load regulation max5803 toc34 v dd = 5v internal reference v ref = 2.048v, 2.5v, 4.096v supply current vs. supply voltage max5803 toc36 input logic voltage (v) supply current (a) 4 3 2 1 200 400 600 800 1000 1200 1400 1600 1800 2000 0 05 v dd = 5v all i/o pins swept v ddio = 5v v ddio = 3v v ddio = 1.8v
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 14 pin configurations pin description pin name function 1 aux active-low auxilliary asynchronous input. user configurable, see table 7. 2 ldac dedicated active-low asynchronous load dac 3 addr i 2 c interface address selection 4 scl i 2 c interface clock input 5 sda i 2 c bidirectional serial data 6 v ddio digital interface power-supply input 7 v dd supply voltage input. bypass v dd with a 0.1ff capacitor to gnd. 8 gnd ground 9 out buffered dac output 10 ref reference voltage input/output ep exposed pad (tdfn only). connect to ground. max5803 max5804 max5805 max580 3 max580 4 max580 5 ref out gnd v dd scl addr ldac aux v ddio sda *connected to gnd top view 1 + 3 4 ref gnd v ddio v dd 2 out aux addr *ep scl ldac tdfn 5 sda 10 8 7 9 6 max + 1 4 5 2 3 10 9 8 7 6 maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 15 detailed description the max5803/max5804/max5805 are single-channel, low-power, 8-/10-/12-bit voltage-output digital-to-analog converters (dacs) with an internal output buffer. the wide supply voltage range of 2.7v to 5.5v and low power consumption accommodate low-power and low- voltage applications. the devices present a 100k i (typ) load to the external reference. the internal output buffer allows rail-to-rail operation. an internal voltage reference is available with software selectable options of 2.048v, 2.500v, or 4.096v. the devices feature a fast 400khz i 2 c-compatible interface. the max5803/ max5804/max5805 include a serial-in/parallel-out shift register, internal code and dac registers, a power-on- reset (por) circuit to initialize the dac output to code zero, and control logic. a user-configurable aux pin is available to asynchronously clear or gate the device output independent of the serial interface. dac output (out) the max5803/max5804/max5805 include an internal buffer on the dac output. the internal output buffer provides improved load regulation for the dac output. the output buffer slews at 1v/fs (typ) and drives up to 2ki in parallel with 500pf. the analog supply voltage (v dd ) determines the maximum output voltage range of the devices as v dd powers the output buffer. under no-load conditions, the output buffer drives from gnd to v dd , subject to offset and gain errors. with a 2ki load to gnd, the output buffer drives from gnd to within and 200mv of v dd . with a 2k i load to v dd , the output buffer drives from v dd to within 200mv of gnd. the dac ideal output voltage is defined by: out ref n d vv 2 = where d = code loaded into the dac register, v ref = reference voltage, n = resolution. internal register structure the user interface is separated from the dac logic to minimize digital feedthrough. within the serial interface is an input shift register, the contents of which can be routed to control registers or the dac itself, as determined by the user command. within the device there is a code register followed by a dac latch register (see the functional diagram). the contents of the code register hold pending dac output settings which can later be loaded into the dac registers. the code register can be updated using both code and code_load user commands. the contents of the dac register hold the current dac output settings. the dac register can be updated directly from the serial interface using the code_load commands or can upload the current contents of the code register using load commands or the ldac input. the contents of both code and dac registers are maintained during all software power-down states, so that when the dac is returned to a normal operating mode, it returns to its previously stored output settings. any code or load commands issued during software power-down states continue to update the register contents. the sw_clear command clears the contents of the code and dac registers to the user-programmable default values. the sw_reset command resets all configuration registers to their power-on default states, while resetting the code and dac registers to zero scale. internal reference the max5803/max5804/max5805 include an internal precision voltage reference that is software selectable to be 2.048v, 2.500v, or 4.096v. when an internal reference is selected, that voltage is available on the ref pin for other external circuitry (see the typical operating circuits) and can drive a 25ki load. external reference the external reference input features a typical input impedance of 100ki and accepts an input voltage from +1.24v to v dd . connect an external voltage supply between ref and gnd to apply an external reference. the max5803/4/5 power up and reset to external reference mode. visit www.maximintegrated. com/products/references for a list of available external voltage-reference devices. aux input the max5803/max5804/max5805 provide an asynchro- nous aux (active-low) input. use the config command to program the device to use the input in one of the fol- lowing modes: clr (default), gate, or disabled. clr mode in clr mode, the aux input performs an asynchronous level sensitive clear operation when pulled low. if clr is configured and asserted, all code and dac maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 16 data registers are cleared to their default/return values as defined by the configuration settings. other user- configuration settings are not affected. some i 2 c interface commands are gated by clr activity during the transfer sequence. if clr is issued during a command write sequence, any gated commands within the sequence are ignored. if clr is issued during an i 2 c command read sequence, the exchange continues as normal, however the data read back may be stale. the user may determine the state of the clr input by issuing a status read. in all cases, the i 2 c interface continues to function according to protocol, however slave ack pulses beyond the command acknowledge are not sent for gated write commands (notifying the fp that these instructions are being ignored). any non- gated commands appearing in the transfer sequence are fully acknowledged and executed. in order for the gating condition to be removed, remove clr prior to a recognized start condition, meeting t clrsta requirements. gate mode use of the gate mode provides a means of momentarily holding the dac in a user-selectable default/return state, returning the dac to the last programmed state upon removal. the max5803/max5804/max5805 also feature a software-accessible gate command. while asserted in gate mode, the aux pin does not interfere with return, code, or dac register updates and related load activity. the user may determine the gate status of the device by issuing a status read. i 2 c readbacks of code and dac register content while gated continue to return the current register values, which may differ from the actual dac output level. ldac input the max5803/max5804/max5805 provide a dedicated asynchronous ldac (active-low) input. the ldac input performs an asynchronous level sensitive load operation when pulled low. use of the ldac input mode provides a means of updating multiple devices together as a group. users wishing to control the dac update instance independently of the i/o instruction should hold ldac high during programming cycles. once programming is complete, ldac may be strobed and the new code register content is loaded into the dac latch output. users wishing to load new dac data in direct response to i/o code register activity should connect ldac permanently low; in this configuration, the max5803/ max5804/max5805 dac output updates in response to each completed i/o code instruction update edge. a software load command is also provided. the ldac operation does not interact with the user interface directly. however, in order to achieve the best possible glitch performance, timing with respect to the interface update edge should follow t ldh specifications when issuing code commands. using the software load command with the broadcast id provides a software-based means of synchronously updating several max5803/max5804/max5805 devices on a shared bus. v ddio input the max5803/max5804/max5805 feature a separate supply pin (v ddio ) for the digital interface (1.8v to 5.5v). if present, connect v ddio to the i/o supply of the host processor. i 2 c serial interface the max5803/max5804/max5805 feature an i 2 c-/ smbusk -compatible, 2-wire serial interface consisting of a serial data line (sda) and a serial clock line (scl). sda and scl enable communication between the max5803/ max5804/max5805 and the master at clock rates up to 400khz. figure 1 shows the 2-wire interface timing diagram. the master generates scl and initiates data transfer on the bus. the master device writes data to the max5803/max5804/max5805 by transmitting the proper slave address followed by the command byte and then the data word. each transmit sequence is framed by a start (s) or repeated start (sr) condition and a stop (p) condition. each word transmitted to the max5803/ max5804/max5805 is 8 bits long and is followed by an acknowledge clock pulse. a master reading data from the max5803/max5804/ max5805 must transmit the proper slave address followed by a series of nine scl pulses for each byte of data requested. the max5803/max5804/max5805 transmit data on sda in sync with the master-generated scl pulses. the master acknowledges receipt of each byte of data. each read sequence is framed by a start or repeated start condition, a not acknowledge, and a stop condition. sda operates as both an input and an open-drain output. a pullup resistor, typically 4.7ki is required on sda. scl operates only as an input. a pullup resistor, typically 4.7k i , is required on scl if there are multiple masters on the bus, or if the single master has an open-drain scl output. maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 17 series resistors in line with sda and scl are optional. series resistors protect the digital inputs of the max5803/ max5804/max5805 from high voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals. the max5803/max5804/max5805 can accommodate bus voltages higher than v dd up to a limit of 5.5v; bus voltages lower than v dd are not recommended and may result in significantly increased interface currents. the max5803/max5804/max5805 digital inputs are double buffered. depending on the command issued through the serial interface, the code register(s) can be loaded without affecting the dac register(s) using the write command. to update the dac registers, either drive the aux input low while in ldac mode to asynchronously update the dac output, or use the software load command. i 2 c start and stop conditions sda and scl idle high when the bus is not in use. a master initiates communication by issuing a start condition. a start condition is a high-to-low transition on sda with scl high. a stop condition is a low-to- high transition on sda while scl is high (figure 2). a start condition from the master signals the beginning of a transmission to the max5803/max5804/max5805. the master terminates transmission and frees the bus by issuing a stop condition. the bus remains active if a repeated start condition is generated instead of a stop condition. i 2 c early stop and repeated start conditions the max5803/max5804/max5805 recognize a stop condition at any point during data transmission except if the stop condition occurs in the same high pulse as a start condition. transmissions ending in an early stop condition do not impact the internal device settings. if stop occurs during a readback byte, the transmission is terminated and a later read mode request begins transfer of the requested register data from the beginning (this applies to combined format i 2 c read mode transfers only, interface verification mode transfers will be corrupted, see figure 2.) i 2 c slave address the slave address is defined as the seven most significant bits (msbs) followed by the r/ w bit. see figure 4 . the five most significant bits are 00110 with the 2 lsbs determined by addr as shown in table 1. setting the r/w bit to 1 configures the max5803/max5804/max5805 for read mode. setting the r/w bit to 0 configures the max5803/max5804/max5805 for write mode. the slave address is the first byte of information sent to the max5803/max5804/max5805 after the start condition. the max5803/max5804/max5805 have the ability to detect an unconnected state on the addr input for additional address flexibility; if leaving the addr input unconnected, be certain to minimize all loading on the pin (i.e. provide a landing for the pin, but do not allow any board traces). using the addr input, up to three devices can be run on a single i 2 c bus figure 2. i 2 c start, repeated start, and stop conditions table 1. i 2 c slave address lsbs a[6:2] = 00110 addr a1 a0 v dd 1 1 n.c. 1 0 gnd 0 0 scl sda ss rp valid start, repeated start, and stop pulses ps p sp p s invalid start/stop pulse pairings - all will be recognized as start s maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 18 i 2 c broadcast address a broadcast address is provided for the purpose of updating or configuring all max5803/max5804/max5805 devices on a given i 2 c bus. all max5803/max5804/ max5805 devices acknowledge and respond to the broadcast device address 00110010. the broadcast mode is intended for use in write mode only (as indicated by r/w = 0 in the address given). i 2 c acknowledge in write mode, the acknowledge bit (ack) is a clocked 9th bit that the max5803/max5804/max5805 use to handshake receipt of each byte of data as shown in figure 3. the max5803/max5804/max5805 pull down sda during the entire master-generated 9th clock pulse if the previous byte is successfully received. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master will retry communication. in read mode, the master pulls down sda during the 9th clock cycle to acknowledge receipt of data from the max5803/max5804/max5805. an acknowledge is sent by the master after each read byte to allow data transfer to continue. a not-acknowledge is sent when the master reads the final byte of data from the max5803/max5804/ max5805, followed by a stop condition. i 2 c command byte and data bytes a command byte follows the slave address. a command byte is typically followed by two data bytes unless it is the last byte in the transmission. if data bytes follow the command byte, the command byte indicates the address of the register that is to receive the following two data bytes. the data bytes are stored in a temporary register and then transferred to the appropriate register during the ack periods between bytes. this avoids any glitching or digital feedthrough to the dac while the interface is active. i 2 c write operations a master device communicates with the max5803/ max5804/max5805 by transmitting the proper slave address followed by command and data words. each transmit sequence is framed by a start or repeated start condition and a stop condition as described above. each word is 8 bits long and is always followed by an acknowledge clock (ack) pulse as shown in figure 4 and figure 5. the first byte contains the address of the max5803/max5804/max5805 with r/w = 0 to indicate a write. the second byte contains the register (or command) to be written and the third and fourth bytes contain the data to be written. by repeating the register address plus data pairs (byte #2 through byte #4 in figure 4 and figure 5), the user can perform multiple register writes using a single i 2 c command sequence. there is no limit as to how many registers the user can write with a single command. the max5803/max5804/ max5805 support this capability for all user-accessible write mode commands. combined format i 2 c readback operations each readback sequence is framed by a start or repeated start condition and a stop condition. each word is 8 bits long and is followed by an acknowledge clock pulse as shown in figure 6. the first byte contains the address of the max5803/max5804/max5805 with r/w = 0 to indicate a write. the second byte contains the register that is to be read back. there is a repeated start condition, followed by the device address with r/w = 1 to indicate a read and an acknowledge clock. the master has control of the scl line but the max5803/ max5804/max5805 take over the sda line. the final two bytes in the frame contain the register data readback followed by a stop condition. if additional bytes beyond those required to readback the requested data are provided, the max5803/max5804/max5805 will continue to readback ones. readback of the return register is supported for the return command (b[23:20] = 0111). readback of the code register is supported for the code command (b[23:20] = 1000). readback of the dac register is supported for all load commands (b[23:20] = 1001, 1010, or 1011). figure 3. i 2 c acknowledge 1 scl start condition sda 29 clock pulse for acknowledgment acknowledge not acknowledge maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 19 readback of all other registers is not directly supported. all requests to read unsupported registers read back the devices current status and configuration settings as shown in table 2. the status register contains information on the current clear, gate, and load status of the device (with a one indicating an asserted status), as well as user configuration settings for the reference, power-down, aux mode, and default operation. interface verification i 2 c readback operations while the max5803/max5804/max5805 support standard i 2 c readback of selected registers, it is also capable of functioning in an interface verification mode. this mode is accessed any time a readback operation follows an executed write mode command. in this mode, the last executed three-byte command is read back in its entirety. this behavior allows verification of the interface. figure 5. multiple register write sequence (standard i 2 c protocol) figure 4. i 2 c single register write sequence scl a w 20 19 18 17 a 16 15 14 13 12 11 10 9a 8 start sda write address byte #1: i 2 c slave address write command byte #2: command byte (b[23:16]) write data byte #3: data high byt e (b[15:8]) write data byte #4: data low byt e (b[7:0]) 21 22 23 stop 7 6 5 4 3 2 1a 0 ack. generated by max5803/max5804 /max5805 command executed 1 0 a1 a0 1 0 0 a scl a w 20 19 18 17 a 16 15 14 13 12 11 10 9a 8 start sda write address byte #1: i 2 c slave address write command1 byte #2: command1 byte (b[23:16]) write data1 byte #3: data1 high byt e (b[15:8]) 21 0 0 1 1 0 a1 a0 22 23 stop 7 6 5 4 3 2 1a 0 write data1 byte #4: data1 low byt e (b[7:0]) 20 19 18 17 a 16 15 14 13 12 11 10 9a 8 21 22 23 7 6 5 4 3 2 1a 0 additional command and data pairs (3 byte blocks) command1 executed commandn executed byte #5: commandn byte (b[23:16]) byte #6: datan high byt e (b[15:8]) byte #7: datan low byt e (b[7:0]) ack. generated by max5803/max5804 / max5805 a maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 20 figure 6. standard i 2 c register read sequence table 2. standard i 2 c user readback data sample command sequences are shown in figure 7. the first command transfer is given in write mode with r/w = 0 and must be run to completion to qualify for interface verification readback. there is now a stop/start pair or repeated start condition required, followed by the readback transfer with r/w = 1 to indicate a read and an acknowledge clock from the max5803/max5804/ max5805. the master still has control of the scl line but the max5803/max5804/max5805 take over the sda line. the final three bytes in the frame contain the command and register data written in the first transfer presented for readback, followed by a stop condition. if additional bytes beyond those required to read back the requested data are provided, the max5803/max5804/max5805 will continue to read back ones. it is not necessary for the write and read mode transfers to occur immediately in sequence. i 2 c transfers involving other devices do not impact the max5803/max5804/ max5805 readback mode. toggling between readback modes is based on the length of the preceding write mode transfer. combined format i 2 c readback operation is resumed if a write command greater than two bytes but less than four bytes is supplied. for commands writ- ten using multiple register write sequences, only the last command executed is read back. for each command written, the readback sequence can only be completed table 3. dac data bit positions command byte (request) readback data high byte readback data low byte b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 x x x x 0 1 0 1 0 rev_id[2:0] (000) part_id[7:0] max5803 = 0x8a max5804 = 0x92 max5805 = 0x82 0 1 1 1 x x x x return[11:4] return[3:0] 0 0 0 0 1 0 0 0 x x x x code[11:4] code[3:0] 0 0 0 0 1 0 0 1 x x x x dac[11:4] dac[3:0] 0 0 0 0 1 0 1 0 x x x x dac[11:4] dac[3:0] 0 0 0 0 1 0 1 1 x x x x dac[11:4] dac[3:0] 0 0 0 0 any other command clr load gate 1 rf[3:0] pd[1:0] ab[2:0] df[2:0] part b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 max5803 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x max5804 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x max5805 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x read data byte #4: data1 high byte (b[15:8]) read data byte #5: data1 lowbyte (b[7:0]) repeated start read address byte #3: i 2 c slave address write address byte #1: i 2 c slave address write command1 byte #2: command1 byte ack. generated by max5803/max5804/max5805 ack. generated by i 2 c master a start stop scl sda 00 11 0a 1a 0w a a a nn n0 01 10 a1 a0 ra dddd dd dd dd dd ddd d ~a a nn nn n maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 21 one time; partial and/or multiple attempts to readback executed in succession will not yield usable data. i 2 c compatibility the max5803/max5804/max5805 are fully compatible with existing i 2 c systems. scl and sda are high- impedance inputs; sda provides an open drain which pulls the data line low to transmit data or ack pulses. figure 8 shows a typical i 2 c application. i 2 c user-command register map this section lists the user-accessible commands and registers for the max5803/max5804/max5805. table 4 provides detailed information about the i 2 c command registers. figure 7. interface verification i 2 c register read sequences scl a w 20 19 18 17 a 16 15 14 13 12 11 10 9 a 8 sda 0 0 1 1 0 a1 a0 22 23 7 6 5 4 3 2 1 a 0 r ~a pointer updated (qualifies for combined read back) command executed (qualifies for interface read back) scl sda command executed (qualifies for interface read back) pointer updated (qualifies for combined read back) 21 a w2 01 91 81 7a 16 15 14 13 12 11 10 9a 8 00 11 0a 1a 02 2 23 76 54 32 1a 0 21 start stop write address byte #1: i 2 c slave address write command byte #2: command byte (b[23:16]) write data byte #3: data high byt e (b[15:8]) write data byte #4: data low byt e (b[7:0]) start stop write address byte #1: i 2 c slave address read command byte #2: command byte (b[23:16]) read data byte #3: data high byt e (b[15:8]) read data byte #4: data low byt e (b[7:0]) start repeated start write address byte #1: i 2 c slave address write command byte #2: command byte (b[23:16]) write data byte #3: data high byt e (b[15:8]) write data byte #4: data low byt e (b[7:0]) stop write address byte #1: i 2 c slave address read command byte #2: command byte (b[23:16]) read data byte #3: data high byt e (b[15:8]) read data byte #4: data low byt e (b[7:0]) ack. generated by max5803/ max5804/ max5805 ack. generated by i 2 c master a2 01 91 81 7a 16 15 14 13 12 11 10 9a 8 00 11 0a 1a 02 2 23 76 54 32 10 21 a r2 01 91 81 7a 16 15 14 13 12 11 10 9a 8 00 11 0a 1a 02 2 23 76 54 32 1~ a 0 21 a a maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 22 code command the code command (b[23:20] = 1000) updates the code register content for the dac. changes to the code register content based on this command will not affect the dac output directly unless the ldac input is in a low state. otherwise, a subsequent hardware or software load operation will be required to move this content to the active dac latch. this command is gated when clr is asserted, updates to this register are ignored while the register is being cleared. see table 3 and table 4. load command the load command (b[23:20] = 1001) updates the dac latch register content by uploading the current contents of the code register. this command is gated when clr is asserted, updates to this register are ignored while the register is being cleared. see table 3 and table 4. code_load command the code_load command (b[23:20] = 1010 and 1011) updates the code register contents as well as the dac register content of the dac. this command is gated when clr is asserted, updates to these registers are ignored while the register is being cleared. see table 3 figure 8. typical i 2 c application circuit c addr scl sda scl sda addr +5v scl sda max5803 max5804 max5805 max5803 max5804 max5805 maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 23 table 4. i 2 c commands summary command b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description dac commands code 1 0 0 0 x x x x code register data[11:4] code register data[3:0] x x x x writes data to the code register load 1 0 0 1 x x x x x x x x x x x x x x x x x x x x transfers data from the code registers to the dac register code_load 1 0 1 0 x x x x code and dac register data[11:4] code and dac register data[3:0] x x x x simultaneously writes data to the code register while updating dac register code_load 1 0 1 1 x x x x code and dac register data[11:4] code and dac register data[3:0] x x x x simultaneously writes data to the code register while updating dac register return 0 1 1 1 x x x x return register data[11:4] return register data[3:0] x x x x updates the return register contents for the dac maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 24 table 4. i 2 c commands summary (continued) command b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description configuration commands ref 0 0 1 0 0 = no drive 1 = drive pin 0 = default 1 = always on ref mode 00 = ext 01 = 2.5v 10 = 2.0v 11 = 4.1v x x x x x x x x x x x x x x x x sets the reference operating mode. software 0 0 1 1 x type: 000 = end 001 = gate 100 = clr 101 = rst other = no effect x x x x x x x x x x x x x x x x executes a software operation of the type chosen power 0 1 0 0 x x x x x x x x x x x x power mode: 00 = dac 01 = 1ki 10 = 100ki 11 = hiz x x x x x x sets the power mode config 0 1 0 1 x x x x x x x x x x x x x x aux mode: 011 = gate 110 = clear 111 = none other = no effect x x x updates the function of the aux input default 0 1 1 0 x x x x x x x x x x x x default values: 000 = por 001 = zero 010 = mid 011 = full 100 = return other = no effect x x x x x sets the default value for the dac no operation commands no operation 0 0 0 0 x x x x x x x x x x x x x x x x x x x x these commands will have no effect on the part. 1 1 1 1 x x x x x x x x x x x x x x x x x x x x reserved commands: any commands not specifically listed above are reserved for maxim internal use only. maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 25 ref command the ref (b[23:20] = 0010) command updates the global reference setting used for the dac. set b[17:16] = 00 to use an external reference for the dac or set b[17:16] to 01, 10, or 11 to select either the 2.5v, 2.048v, or 4.096v internal reference, respectively. if rf3 (b19) is set to zero (default) in the ref command, the ref i/o will not be driven by the internal reference circuit, saving current. if rf3 is set to one, the ref i/o will be driven by the internal reference circuit, consuming an additional 25 f a (typ) of current when the reference is powered; when the reference is powered down, the ref i/o will be high-impedance. if rf2 (b18) is set to zero (default) in the ref command, the reference will be powered down any time the dac is powered down (in standby mode). if rf2 (b18) is set to one, the reference will remain powered even if the dac is powered down, allowing continued operation of external circuitry. in this mode, the 1 f a shutdown state is not available. see table 5. software commands the software (b[23:20] = 0011) commands provide a means of issuing several flexible software actions. see table 6. the software command action mode is selected by b[18:16]: end (000): used to end any active gate operation, returning to normal operation (default). gate (001): dac contents will be gated to their default selected values until the gate condition is removed. clear (100): all code and dac contents will be cleared to their default selected values. reset (101): all code, dac, return, and configuration registers reset to their power-up defaults (including ref, power, and config settings), simulating a power cycle reset. other: no effect. table 5. ref (0010) command format table 6. software (0011) command format b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 0 rf3 rf2 rf1 rf0 x x x x x x x x x x x x x x x x ref command 0 = ref not driven 1 = ref driven 0 = off in standby 1 = on in standby ref mode: 00 = ext 01 = 2.5v 10 = 2.0v 11 = 4.0v dont care dont care default values 0 0 0 0 x x x x x x x x x x x x x x x x command byte data high byte data low byte b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 1 x sw2 sw1 sw0 x x x x x x x x x x x x x x x x software commands dont care mode: 000: end 001: gate 100: clr 101: rst other: no effect dont care dont care default values x 0 0 0 x x x x x x x x x x x x x x x x command byte data high byte data low byte maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 26 table 7. power (0100) command format table 8. selectable dac output impedance in power-down mode power command the max5803/max5804/max5805 feature a software- controlled power mode command (b[23:20] = 0100). in power-down, the dac output is disconnected from the buffer and is grounded with either one of the two selectable internal resistors or set to high impedance. see table 7 and table 8 for the selectable internal resistor values in power-down mode. in power-down mode, the dac register retains its value so that the output is restored when the device powers up. the serial interface remains active in power-down mode with all registers accessible. in power-down mode, the internal reference can be powered down or it can be set to remain powered-on for external use. also, in power-down mode, parts using the external reference do not load the ref pin. see table 7. b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 0 x x x x x x x x x x x x pd1 pd0 x x x x x x power command dont care dont care power mode: 00 = normal 01 = 1ki 10 = 100ki 11 = hi-z dont care default values x x x x x x x x x x x x 0 0 x x x x x x command byte data high byte data low byte pd1 (b7) pd0 (b6) operating mode 0 0 normal operation 0 1 power-down with internal 1ki pulldown resistor to gnd. 1 0 power-down with internal 100ki pulldown resistor to gnd. 1 1 power-down with high-impedance output. maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 27 config command the config command (b[23:20] = 0101) updates the function of the aux input enabling its gate or clear (default) operation mode. see table 9. aux config settings are written by b[5:3]: gate (011): aux functions as a gate . dac code is gated to default value input when pin is low. clear (110): aux functions as a clr input (default). code and dac content is cleared to default value if pin is low. none (111): aux functions are disabled. other: aux function is not altered. default command default (0110): the default command selects the default value for the dac. these default values are used for all future clear and gate operations. the new default setting is determined by bits df[2:0]. see table 10. available default values are: por (000): dac defaults to power-on reset value (default). zero (001): dac defaults to zero scale. mid (010): dac defaults to midscale. full (011): dac defaults to full scale. return (100): dac defaults to value specified by the return register other: no effect, the default setting remains unchanged. note: the selected default values do not apply to resets initiated by sw_reset commands or supply cycling, both of which return the dacs to the power-on reset state (zero scale). table 9. config (0101) command format table 10. default (0110) command format b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 1 0 x x x x x x x x x x x x df2 df1 df0 x x x x x default command dont care dont care default values: 000: por 001: zero 010: mid 011: full 100: return other: no effect dont care default values x x x x x x x x x x x x 0 0 0 x x x x x command byte data high byte data low byte b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 1 x x x x x x x x x x x x x x ab2 ab1 ab0 x x x config command dont care dont care dont care auxb mode: 011 = gate 110 = clear 111 = none other = no effect dont care default values x x x x x x x x x x x x x x 1 1 0 x x x command byte data high byte data low byte maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 28 return command the return command (b[23:20] = 0111) updates the return register content for the dac. if the default configuration register is set to return mode, the dac will be cleared or gated to the return register value in the event of a sw or hw clear or gate condition. it is not necessary to program this register if the default = return mode will not be used. the data format for the return register is identical to that used for code and load operations. see table 3 and table 4. applications information power-on reset (por) when power is applied to v dd , the dac output is set to zero scale. to optimize dac linearity, wait until the supplies have settled and the internal setup and calibration sequence completes (200fs, typ). power supplies and bypassing considerations bypass v dd with high-quality ceramic capacitors to a low-impedance ground as close as possible to the device. minimize lead lengths to reduce lead inductance. connect gnd to the analog ground plane. layout considerations digital and ac transient signals on gnd can create noise at the output. connect gnd to form the star ground for the dac system. refer remote dac loads to this system ground for the best possible performance. use proper grounding techniques, such as a multilayer board with a low-inductance ground plane, or star connect all ground return paths back to the max5803/max5804/ max5805 gnd. carefully layout the traces between channels to reduce ac cross-coupling. do not use wire- wrapped boards and sockets. use shielding to maximize noise immunity. do not run analog and digital signals parallel to one another, especially clock signals. avoid routing digital lines underneath the max5803/max5804/ max5805 package. definitions integral nonlinearity (inl) inl is the deviation of the measured transfer function from a straight line drawn between two codes once offset and gain errors have been nullified. differential nonlinearity (dnl) dnl is the difference between an actual step height and the ideal value of 1 lsb. if the magnitude of the dnl p 1 lsb, the dac guarantees no missing codes and is monotonic. if the magnitude of the dnl r 1 lsb, the dac output may still be monotonic. offset error offset error indicates how well the actual transfer function matches the ideal transfer function. the offset error is calculated from two measurements near zero code and near maximum code. gain error gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same percentage error in each step. zero-scale error zero-scale error is the difference between the dac output voltage when set to code zero and ground. this includes offset and other die level nonidealities. full-scale error full-scale error is the difference between the dac output voltage when set to full scale and the reference voltage. this includes offset, gain error, and other die level nonidealities. settling time the settling time is the amount of time required from the start of a transition, until the dac output settles to the new output value within the converters specified accuracy. digital feedthrough digital feedthrough is the amount of noise that appears on the dac output when the dac digital control lines are toggled. digital-to-analog glitch impulse a major carry transition occurs at the midscale point where the msb changes from low to high and all other bits change from high to low, or where the msb changes from high to low and all other bits change from low to high. the duration of the magnitude of the switching glitch during a major carry transition is referred to as the digital-to-analog glitch impulse. the digital-to-analog power-up glitch is the duration of the magnitude of the switching glitch that occurs as the device exits power-down mode. maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 29 typical operating circuits micro - controller sda scl addr out gnd ref 4.7f 100nf 100nf r1 r2 r1 = r2 aux r pu 5ki r pu 5ki note: bipolar operation shown dac v dd max5803 max5804 max5805 4.7f 100nf micro - controller sda scl addr out gnd ref 100nf aux ldac r pu 5ki r pu 5ki note: unipolar operation shown dac v dd v ddio max5803 max5804 max5805 v ddio v out = -v ref to +v ref v out = 0v to v ref ldac maxim integrated
max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface 30 chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. ordering information note: all devices are specified over the -40c to +125c temperature range. +denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. *ep = exposed pad. part pin-package resolution (bit) internal reference tempco (ppm/nc) max5803atb+t 10 tdfn-ep* 8 10 (typ), 25 (max) MAX5803AUB+ 10 fmax 8 10 (typ), 25 (max) max5804atb+t 10 tdfn-ep* 10 10 (typ), 25 (max) max5804aub+ 10 fmax 10 10 (typ), 25 (max) max5805aaub+ 10 fmax 12 4 (typ), 12 (max) max5805batb+t 10 tdfn-ep* 12 10 (typ), 25 (max) max5805baub+ 10 fmax 12 10 (typ), 25 (max) package type package code outline no. land pattern no. 10 tdfn-ep t1032n+1 21-0429 90-0082 10 fmax u10+2 21-0061 90-0330 maxim integrated
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 31 ? 2013 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 11/12 initial release 1 2/13 released the max5803/max5804. updated the electrical characteristics. 2C8, 30 2 6/13 released the max5803/max5804/max5805 tdfn packages. 30 max5803/max5804/max5805 ultra-small, single-channel, 8-/10-/12-bit buffered output voltage dacs with internal reference and i 2 c interface

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